1. Technical Field
Embodiments of this disclosure relate generally to a semiconductor device and methods of operating the same and, more particularly, to a program method.
2. Related Art
A semiconductor device includes a memory cell array in which data is stored. The memory cell array includes a plurality of cell blocks. Each of the cell blocks includes a plurality of cell strings. The cell strings have the same structure, and thus, only one of the cell strings is described below in detail.
FIG. 1 is a circuit diagram illustrating a cell string.
Referring to FIG. 1, the cell string includes a drain select transistor, a plurality of memory cells, and a source select transistor which are coupled in series. The gate of the drain select transistor is coupled to a drain select line DSL, the gates of the memory cells are coupled to respective word lines WLn−k to WLn+k (i.e., WLn−k, WLn−2 WLn−1, WLn, WLn+1, WLn+2, . . . , WLn+k), and the gate of the source select transistor is coupled to a source select line SSL. The drain select line DSL is coupled in common to the drain select transistors included in different cell strings. The word lines WLn−k to WLn+k are coupled in common to the memory cells included in different cell strings. The source select line SSL is coupled in common to the source select transistors included in different cell strings.
A method of programming a memory cell selected from among the memory cells included in the cell string is described below.
A program voltage Vpgm is supplied to a selected word line WLn coupled to a selected memory cell 11. A pass voltage Vpass is supplied to unselected word lines WLn−1 to WLn−k and WLn+1 to WLn+k coupled to unselected memory cells. The selected memory cell 11 may be programmed by supplying the program voltage Vpgm to the selected word line WLn only once. In order to narrow the width of a distribution of the threshold voltages of memory cells, however, the program operation is recently performed in accordance with an Incremental Step Pulse Program (hereinafter referred to as an ‘ISPP’) method of gradually raising the program voltage Vpgm. The program operation using an ISPP method is described below.
FIG. 2 is a graph illustrating a known program method.
Referring to FIGS. 1 and 2, a program operation using an ISPP method is performed by supplying the program voltage Vpgm to the selected word line WLn and supplying a constant pass voltage Vpass(1) or an increasing pass voltage Vpass(2) to the remaining unselected word lines WLn−1 to WLn−k and WLn+1 to WLn+k. The increasing pass voltage Vpass(2) increases as a step-up level lower than that of the program voltage Vpgm. In general, the constant pass voltage Vpass(1) or the increasing pass voltage Vpass(2) has a level lower than the program voltage Vpgm. More particularly, the program voltage Vpgm having a low level is supplied at the early stage of program, and the program voltage Vpgm having a gradually higher level is supplied according to an increase in the number of program voltages Vpgm. After the program voltage Vpgm and the constant pass voltage Vpass(1) or the increasing pass voltage Vpass(2) are supplied, a verify operation for determining whether the threshold voltage of the selected memory cell has reached a target voltage is performed. If, as a result of the verify operation, the threshold voltage of the selected memory cell is determined not to have reached the target voltage, the program operation and the verify operation are repeated by supplying the program voltage Vpgm and the constant pass voltage Vpass(1) or the increasing pass voltage Vpass(2) while gradually raising the program voltage Vpgm by a step level until the threshold voltage of the selected memory cell reaches the target voltage. If, as a result of the verify operation, the threshold voltage of the selected memory cell is determined to have reached the target voltage, the program operation is terminated.
While the program operation is performed, the program voltage Vpgm is gradually raised, whereas the constant pass voltage Vpass(1) or the increasing pass voltage Vpass(2) is supplied to the unselected word lines WLn−1 to WLn−k and WLn+1 to WLn+k. Accordingly, a difference in the level between the program voltage Vpgm and the constant pass voltage Vpass(1) or the increasing pass voltage Vpass(2) is gradually increased.
Particularly, in case of an unselected memory cells 12 adjacent to the selected memory cell 11, if the level of the program voltage Vpgm supplied to the selected word line WLn is higher than a specific level, the threshold voltages of the unselected memory cells 12 may be decreased under the influence of the raised program voltage Vpgm. That is, if the program voltage Vpgm gradually rises and becomes higher than a Critical voltage Difference (hereinafter referred to as a ‘CD’) between the program voltage Vpgm and the pass voltage Vpass, a breakdown between the unselsected memory cells 12 and the selected memory cells 11 may be occurred. Furthermore, electrons which are stored in a floating gate of the unselected memory cells 12 adjacent to the selected memory cell 11 may eject to a control gate of the selected memory cell 11, and so the threshold voltages of the unselected memory cells 12 may decrease. In particular, if the threshold voltage of a memory cell on which program has been completed, from among the unselected memory cells 12 adjacent to the selected memory cell 11, is changed, different data may be read from the memory cell on which a program has been completed in a read operation. Consequently, the reliability of the semiconductor device may deteriorate.